This application relies for priority upon Korean Patent Application No. 2001-46234, filed on Jul. 31, 2001, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to semiconductor devices and fabrication methods thereof. More particularly, it relates to floating trap type non-volatile memory devices and to fabrication methods thereof.
A non-volatile memory device retains information stored in its memory cells even when no power is supplied. Nowadays, the non-volatile memory device is widely used in various kinds of electronic products such as cellular phones, memory cards, and so on. Generally, the non-volatile memory device has been classified as either a floating gate type device or a floating trap type device.
The floating gate type device comprises a tunneling layer, a floating gate electrode, an inter-poly dielectric layer and a control gate electrode, which are sequentially stacked on a semiconductor substrate. The floating gate type device stores charge in the floating gate electrode as free carriers. Accordingly, the entire memory charge stored in the floating gate electrode may be unfavorably discharged through even a single defect in the tunneling layer, which is usually formed of silicon oxide. The concern over the loss of the entire memory charge limits vertical scaling of the tunneling layer of the floating gate type device. In other words, in the floating gate type device, a relatively thick tunneling layer is preferably required. However, the thick tunneling layer may induce several disadvantages, for example, fluctuation of threshold voltage, high operating voltage or high power consumption.
On the other hand, the floating trap type device comprises a tunneling layer, a charge storage layer, a blocking layer and a gate electrode, which are sequentially stacked on a semiconductor substrate. The floating trap type device stores charge in a spatially isolated deep level trap of the charge storage layer. Accordingly, there is substantially no concern over the loss of the memory charge, and a relatively thin tunneling layer is applicable with an operating voltage as low as 5xcx9c10 V.
In view of fabrication processes, the floating trap type device can be fabricated more easily than the floating gate type device. This is because the floating trap type device requires no floating gate electrode so that the structure thereof is relatively simple.
One typical example of the floating trap type device is a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) non-volatile memory device. FIG. 1 is cross-sectional view illustrating a unit cell of the conventional SONOS device. An isolation region 12 is formed on a portion of a silicon substrate 10, thereby defining an active region on the other portion of the silicon substrate 10. Impurity doped regions 28 are formed in the active region. A tunneling layer 20, a charge storage layer 22 and a blocking layer 24 are stacked sequentially on the active region. On the blocking layer 24, a gate electrode 27 is formed. The tunneling layer 20 is formed of thermally grown oxide. The charge storage layer 22 is formed of silicon nitride. Though not shown in the drawing, the isolation region 12 is formed by a self-aligned trench isolation technique. The gate electrode 27 comprises a lower gate electrode 25 and an upper gate electrode 26.
FIG. 2 is a band diagram taken along a line I-Ixe2x80x2 of FIG. 1. Silicon nitride, the material of the charge storage layer 22, has an energy band gap of approximately 5 eV. Reference symbol Ø1 and Ø2 indicate potential barriers between the charge storage layer 22 and the tunneling layer 20 in a conduction band and a valance band, respectively. Potential barrier Ø1 is approximately 1 eV and Potential barrier Ø2 is approximately 2 eV.
The charge storage layer 22, silicon nitride, is known to have three kinds of trap levels within the energy band gap. The trap center of silicon nitride is a silicon atom having a dangling bond and three other bonds. Each of the three other bonds is attached to a nitrogen atom. A first trap level E1 represents a state where a hole is attached to the dangling bond. A second trap level E2 represents a state where a single electron is attached to the dangling bond. The second trap level E2 is higher than the first trap level E1. A third trap level E3 represents a state where two electrons are attached to the dangling bond. The third trap level E3 is higher than the second trap level E2.
When a positive voltage is applied to the gate electrode 27, electrons are captured into the traps of the charge storage layer 22 by tunneling through the tunneling layer 20. The trapped electrons result in an increased threshold voltage and the cell attains a programmed state. When a negative voltage is applied to the gate electrode 27, the captured electrons are removed from the charge storage layer 22 by another tunneling into the substrate 10 through the tunneling layer 20, and the cell attains an erased state.
However, the SONOS devices have a problem, which results from their non-ideal charge retention characteristic. The SONOS devices cannot retain the charges stored in the charge storage layer 22 for a reasonable period of time. That is to say, the SONOS devices lose the information stored in the cell too readily under a date retention mode. FIG. 3 is a band diagram illustrating a charge loss mechanism of the SONOS devices. As depicted in the drawing, the energy band diagram of the SONOS device has an inclined portion. This is because the charges trapped in the charge storage layer 22 induce an internal electric field under the date retention mode. The charge loss mechanism of the SONOS device will be described as following.
Reference number 1 in FIG. 3 indicates a first charge loss path. In the first charge loss path, the trapped electrons at the third trap level E3 are thermally excited to the conduction band of the charge storage layer 22. The excited electrons subsequently tunnel into the substrate 10 through the tunneling layer 20 under the influence of the internal electric field. Reference number 2 in FIG. 3 indicates a second charge loss path. In the second charge loss path, the trapped electrons are removed into the substrate 10 through the tunneling layer 20 by a band-to-band-tunneling. The electrons trapped at the higher third trap level E3 can readily tunnel through the trapezoidal-shape barrier 5 of the tunneling layer 20. Reference number 3 in FIG. 3 indicates a third charge loss path. The third charge loss path is called trap-assisted-tunneling. The trap-assisted-tunneling occurs by the way of bulk traps 6 of the tunneling layer 20 and boundary regions between the tunneling layer 20 and the substrate 10. The electrons trapped even in the lower second trap level E2 can readily tunnel into the substrate 10. Reference number 4 in FIG. 3 indicates a forth charge loss path. In the forth charge loss path, holes in the valence band of the substrate 10 tunnel through the tunneling layer 20 and are captured at the first trap level E1 of the charge storage layer 22.
The conventional SONOS devices have received limited commercial acceptance in industry due to the poor charge retention characteristic as described above. Accordingly, the need for floating trap type non-volatile memory devices having improved charge retention characteristic remains.
It is an object of the present invention to provide a semiconductor device having a gate electrode, a blocking layer, a charge storage layer and a tunneling layer, wherein a probability of charge loss is decreased by an increased potential barrier between the charge storage layer and the tunneling layer.
It is another object of the present invention to provide a semiconductor device having a gate electrode, a blocking layer, a charge storage layer and a tunneling layer, wherein tunneling from the charge storage layer into the gate electrode is suppressed.
It is another object of the present invention to provide a semiconductor device having a gate electrode, a blocking layer, a charge storage layer and a tunneling layer, wherein charge retention characteristic is improved.
According to one aspect of the present invention, a semiconductor device is provided. The semiconductor device comprises a substrate, a gate electrode formed on the substrate and a charge storage layer interposed between the substrate and the gate electrode. The charge storage layer comprises an electrical insulating layer. The material used for the electrical insulating layer has a narrower band gap than silicon nitride. The electrical insulating layer is preferably formed of tetrahedral amorphous carbon.
The semiconductor device also comprises a blocking layer interposed between the gate electrode and the charge storage layer, a tunneling layer interposed between the substrate and the charge storage layer, and an impurity doped region in the substrate and adjacent an end of the gate electrode. The blocking layer is formed of CVD oxide. The tunneling layer is formed of thermally grown oxide. The gate electrode comprises a polysilicon layer.
According to another aspect of the present invention, a semiconductor device is provided. The semiconductor device comprises a substrate, a gate electrode formed on the substrate, and a charge storage layer interposed between the substrate and the gate electrode. The charge storage layer comprises a plurality of electrical insulating layers. The material of at least one of the plurality of electrical insulating layers has a narrower band gap than silicon nitride, and is preferably formed of tetrahedral amorphous carbon. The semiconductor device also comprises a blocking layer interposed between the gate electrode and the charge storage layer, a tunneling layer interposed between the substrate and the charge storage layer, and an impurity doped region in the substrate and adjacent an end of the gate electrode. The blocking layer is formed of CVD oxide. The tunneling layer is formed of thermally grown oxide. The gate electrode comprises a polysilicon layer. The charge storage layer may comprise a first charge storage layer formed on the substrate, a second charge storage layer formed on the first charge storage layer. The second charge storage layer has a narrower band gap than the first charge storage layer. The first charge storage layer is formed of silicon nitride or silicon oxynitride. The second charge storage layer is formed of tetrahedral amorphous carbon. The semiconductor device may further comprise a third charge storage layer. The second charge storage layer has a narrower band gap than the third charge storage layer. The third charge storage layer is formed of silicon nitride or silicon oxynitride.